
The Inter-Integrated Circuit (I2C) is a communication bus that allows multiple peripheral digital integrated circuits (chips) to communicate with one or more controller chips. I2C is a serial communication protocol, meaning it transfers data bit by bit along a single wire.
I2C is widely used for attaching lower-speed peripheral integrated circuits (ICs) to processors and microcontrollers in short-distance, intra-board communication. It is commonly used for reading hardware monitors, sensors, real-time clocks, controlling actuators, accessing low-speed DACs and ADCs, controlling simple LCD or OLED displays, and changing computer display settings.
I2C uses only two wires for data transmission: a serial data line (SDA) and a serial clock line (SCL). Both are bidirectional and pulled up with resistors. The SCL line is always generated by the current bus controller and is used to synchronize the data transfer between devices. The SDA line carries the data.
Each device on the I2C bus has a preset ID or unique device address, allowing the master to choose which devices to communicate with. Data is transferred in sequences of 8 bits, with a special start and stop condition indicating the beginning and end of a transmission.
I2C communication protocol
The Inter-Integrated Circuit (I2C) Protocol is a communication protocol that allows multiple "peripheral" digital integrated circuits or "chips" to communicate with one or more "controller" chips. It is a serial communication protocol, meaning data is transferred bit by bit along a single wire.
I2C combines the best features of SPI and UARTs. With I2C, you can connect multiple slaves to a single master and have multiple masters controlling single or multiple slaves. This is particularly useful when you want to have more than one microcontroller logging data to a single memory card or displaying text on a single LCD.
I2C only uses two wires to transmit data between devices:
- SDA (Serial Data) — The line for the master and slave to send and receive data.
- SCL (Serial Clock) — The line that carries the clock signal, always controlled by the master.
Messages are broken up into frames of data. Each message has an address frame that contains the binary address of the slave, and one or more data frames that contain the data being transmitted. The message also includes start and stop conditions, read/write bits, and ACK/NACK bits between each data frame.
The start condition occurs when the SDA line switches from a high voltage level to a low voltage level before the SCL line switches from high to low. The master sends the address of the slave it wants to communicate with to every slave connected to it. Each slave then compares the address sent from the master to its own address. If the address matches, it sends an ACK bit back to the master, and the first data frame is ready to be sent.
The data frame is always 8 bits long and is sent with the most significant bit first. Each data frame is immediately followed by an ACK/NACK bit to verify that the frame has been received successfully. After all the data frames have been sent, the master can send a stop condition to the slave to halt the transmission.
I2C supports a multi-controller bus, meaning any number of controller nodes can be present. Additionally, controller and target roles may be changed between messages. The protocol also allows for clock stretching and arbitration, ensuring smooth communication between devices.
I2C is widely used for attaching lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication. It is commonly found in PC components, sensors, displays, and other electronics applications where simplicity and low manufacturing cost are prioritised over speed.
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I2C bus drivers
In the case of I2C, the signal lines are pulled high by using pull-up resistors. This means that the bus drivers only need to pull the signal line low, and the pull-up resistors will take care of pulling the signal line high when it is not being driven low.
The use of open-drain bus drivers in I2C has several advantages. Firstly, it eliminates the potential for bus contention, where two devices try to drive the signal line in opposite directions at the same time, which can lead to damage or excessive power dissipation. Secondly, it allows for some flexibility in connecting devices with different I/O voltages. Since the devices on the bus don't actually drive the signals high, it is possible to connect devices with different I/O voltages without the need for level-shifting circuitry, as long as the pull-up resistors are connected to the lower of the two voltages.
The typical voltages used for I2C bus drivers are +5V or +3.3V, although systems with other voltages are permitted. The choice of pull-up resistor values depends on the speed of the bus and the number of devices connected. For higher speeds of around 400 kbps, lower resistor values such as 2K are recommended, while for lower speeds of around 100 kbps, higher resistor values such as 10K can be used.
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I2C bus speeds
The I2C bus defines several speed grades, including standard mode (100 kbit/s), full speed (400 kbit/s), fast mode (1 Mbit/s), and high speed (3.2 Mbit/s). These speed grades are maximum ratings, meaning that compliant hardware guarantees it can handle transmission speeds up to the maximum clock rate specified by the mode. However, it is good practice for any device to read back the logic level of a modified line (both clock and data) before proceeding with further actions. This is because the I2C bus uses open-drain technology, where the bus is kept on a high level, and writing to the bus means pulling its level to the ground.
The I2C bus is intended for inter-IC communication, which usually involves small data packets. Since the timing can never be determined exactly and the transmitted information is often short, the accuracy of the bus clock is often irrelevant in most applications.
The length of data messages also affects the relationship between clock speed and bus data transfer speed. Except for the overhead required for start and stop conditions, acknowledge bits, and device addresses, the clock speed and bus data transfer speed are the same. Therefore, the more data that is sent per message, the closer the data rate will be to the clock speed. For instance, for very short messages (one address byte and one data byte), the data rate will be a little less than 50% of the clock rate, whereas for very long messages, it will be more like 90%.
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I2C hardware
The Inter-Integrated Circuit (I2C) bus consists of two signals: SDA (Serial Data) and SCL (Serial Clock). SDA is the data signal, and SCL is the clock signal, which is always generated by the current bus controller. The I2C bus drivers are "open drain", meaning they can only pull the corresponding signal line low, not drive it high. This prevents bus contention, where one device tries to drive the line high while another tries to pull it low, which could damage the drivers or cause excessive power dissipation in the system. Each signal line has a pull-up resistor to restore the signal to high when no device is asserting it low.
The I2C protocol is notable for its complexity, which allows for features such as the concurrent operation of multiple I2C masters and "clock stretching" (where slave devices can slow down communication by holding SCL low). Every device on the bus must connect to both the clock and data signals via open-drain output drivers. The signals always default to logic high, and any device can safely drive the signals to logic low.
The I2C bus can be used with short runs of wire (2-3m) and can support up to 1008 peripheral devices. It is a fairly robust protocol and offers some flexibility in connecting devices with different I/O voltages.
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I2C software
For instance, the SoftwareI2C library is designed to work with Arduino when the I2C pins are already in use for other purposes or when using devices with the same I2C addresses. It allows multiple devices with the same I2C addresses to work on Arduino by utilising the digital port and analog port.
The SoftI2CMaster library, adapted from Peter Fleury's I2C software library, is advantageous when facing limitations with the Wire library, such as I2C pins SDA/SCL being in use, memory constraints, or the need to disable implicitly enabled pull-up resistors for 3.3-volt devices. This library is compatible with all 8-bit AVR MCUs, supports master mode only, and offers a lightweight and fast solution.
SoftWire, another software I2C implementation for Arduino and Wiring-type environments, also utilises the pinMode(), digitalWrite(), and digitalRead() functions. It supports multiple software I2C buses and clock-stretching by slave devices. Additionally, it includes a timeout feature to prevent lockups caused by faulty or missing hardware.
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Frequently asked questions
I2C (Inter-Integrated Circuit) is a communication bus that allows multiple "peripheral" digital integrated circuits ("chips") to communicate with one or more "controller" chips.
I2C combines the best features of SPI and UARTs. With I2C, you can connect multiple slaves to a single master and have multiple masters controlling single or multiple slaves. It is widely used for attaching lower-speed peripheral integrated circuits (ICs) to processors and microcontrollers in short-distance, intra-board communication.
I2C uses only two signals: serial data line (SDA) and serial clock line (SCL). Both are bidirectional and pulled up with resistors. The master device generates the clock signal and initiates communication with the target devices (slaves). The master sends the target's address, which responds with an ACK bit if it exists on the bus. The master then sends or receives data, with each byte followed by an ACK/NACK bit to confirm successful transmission.